Static random access memory (SRAM) is a type of semiconductor memory that stores data in the form of bits using bistable circuitry without the need for refreshing. An SRAM cell may be referred to as a bit cell because it stores a bit of information. Each bit cell in a memory array typically includes connections to a power supply voltage and to a reference voltage. Bit lines are used for accessing a bit cell, with a word line controlling connections to the bit lines. The lowest VDD voltage (positive power supply voltage) at which an SRAM bit cell may function is referred to as Vccmin. One issue as CMOS technology scales down is the choice of an appropriate power supply level. Increasing the power supply level may yield faster performance and improved reliability for memory cells and word line drivers that interface with memory cells. On the other hand, increasing the power supply level may increase leakage for other components.
One approach that has been used as SRAM area scales down is referred to as dual rail SRAM, in which dual power rails are provided. A power supply voltage VDD is provided for certain components (e.g., components preceding and including a level shifter in a processing flow), and another power supply voltage CVDD (which stands for “cell VDD”) greater than VDD is provided for memory cells and word line drivers. A level shifter may be included at any stage before word line drivers to shift the voltage level from VDD to CVDD. With dual rail SRAM, faster performance and improved reliability for memory cells and word line drivers may be achieved without unduly increasing leakage for other components.